Voltage islands, that is areas on a VLSI chip having different voltages applied for the sole purpose of power reduction, are becoming more prevalent. In some cases these islands are large, distinct physical entities that have only a limited number of physical interfaces, but for the cases where the islands are more like islets, there are a number of physical issues that must be addressed.
Circuits, whether associated with an ASIC, foundry, or custom logic, attempt to maximize area efficiency. One such approach is the sharing of physical domains such as Nwells, Pwells or substrates. For the case of an Nwell process wherein the pfets are contained in an Nwell, the Nwell generally is biased to Vdd and is shared across two circuit rows, and in general, is contiguous within a row. To support a lower, alternate vdd, Vddl, as well as the standard or higher vdd, one is faced with the placement dilemma of Nwell proximity. If each Nwell is biased to its respective power rail, then row pairs must be first identified as requiring either a Vddl or Vdd Nwell bias. This limits placement as will be illustrated later. If, however, a common Nwell biasing scheme were to be employed, as is the premise of this disclosure, then placement could be handled independent of well placements.
To further illustrate these issues, refer now to the following description in conjunction with the accompanying figures. FIG. 1 illustrates a conventional standard cell configuration 10. This configuration 10 is generally mirrored about the x-axis to allow sharing of Nwells 12 and substrates. The Nwell 12 is either biased to Vddh 14 within a given circuit, or a separate Nwell tap cell is inserted between circuits.
FIG. 2 represents a pair of circuits comprising mirror flipped circuits 100 which create two circuit placement rows. In this figure the common Nwell 102 is associated with the mirror-flipped circuit pairs, each of which is biased to Vddh 106. FIG. 3 illustrates a four-row circuit placement 200 with shared Nwells 202a and 202b and common power supply rails Vddh 206. Circuit rows 1 and 2, and 3 and 4 each share their respective Nwells 202a and 202b. For any of these configurations, physical layout ground rules for Nwells 202a and 202b are generally rather large. The typical NW to NW space is generally more than twice the metal-2 pitch. That means that if two circuits were to be placed in a common row with differently biased Nwells, that a minimum of 3-wiring tracks would have to be left vacant. This represents a rather large unused area on a VLSI circuit.
FIG. 4 illustrates voltage island cell arrangement 300 for non-common Nwell biasing between islands. Rows 1 and 2 are associated with two distinct power domains in the leftmost island rows 1 and 2, share a common Vddh 306 (i.e., 5V) and in the rightmost island rows 1 and 2 have a common Vddl 308 (i.e., 3V). In this arrangement, the area within each island can be used relatively effectively. However, if the biasing schemes for Nwells 302a and 302b are different, Nwell sharing between these distinct Nwells is not possible.
FIG. 5 illustrates the effect of not supporting common biased Nwells for placements. In this figure, as is seen, large placement voids result. The other alternative is that circuits having common Nwells might be placed in those regions even if those regions were not the best locations from a wiring perspective.
Accordingly, what is needed is a common Nwell implementation which will result in the most area efficiency and will reduce leakage current. The present invention addresses such a need.